1. Field of the Invention
The present invention is related to a delay method and device, and more particularly, to a delay method and device for delaying activation timing of an output device.
2. Description of the Prior Art
A Universal Serial Bus (USB) is a convenient and economic solution for electrical connection, especially for “hot attach and detach” and “plug and play” applications. Characterized by expansibility, easy installation and high transmission rate, the USB is widely employed in computer systems, and is utilized for connecting the computer systems with USB peripherals, such as a keyboard, mouse, portable hard disk, compact disc read-only memory (CD-ROM) drive, joystick, printer, scanner, etc.
Please refer to FIG. 1A, which is a schematic diagram of a circuit system 10 of the prior art. The circuit system 10 is generally installed on a main board of a computer system to provide power conforming to USB standards. The circuit system 10 includes a power end PWR, switch units 100_1, 100_2, 100_3, 100_4, a control unit 110 and output ports USB[1], USB[2], USB[3], USB[4]. When the computer system is powered on, the control unit 110 generates an enable signal ENB to respectively indicate to the switch units 100_1, 100_2, 100_3, 100_4 to connect the power end PWR and the output ports USB[1], USB[2], USB[3], USB[4], so as to provide output voltages Vo[1], Vo[2], Vo[3], Vo[4] according to a supply voltage VCC received by the power end PWR and charge output capacitors C_1, C_2, C_3, C_4. As a result, the output voltages Vo[1], Vo[2], Vo[3], Vo[4] can be respectively transmitted to external electronic devices via the output ports USB[1], USB[2], USB[3], USB[4].
To protect the circuit system 10, each of the switch units 100_1, 100_2, 100_3, 100_4 is installed with an over-current signal end OC coupled to the power end PWR via an over-current flag pull-high resistor (ROC1, ROC2, ROC3 or ROC4) and utilized for informing the circuit system if an over-current condition is triggered, so as to prevent the circuit system 10 and the external electronic devices from burnout induced by overloaded currents. That is, the over-current flag pull-high resistors ROC1, ROC2, ROC3, ROC4 function as current sources capable of pulling high voltages of the over-current signal ends OC.
When all the output ports USB[1], USB[2], USB[3], USB[4] are connected to external electronic devices, the circuit system 10 may break down, since current demand explodes. Please refer to FIG. 1B, which is a timing diagram of related signals when the circuit system 10 is powered on. In FIG. 1B, the enable signal ENB indicates to the switch units 100_1, 100_2, 100_3, 100_4 to start operating at a time t0, and accordingly the output voltages Vo[1], Vo[2], Vo[3], Vo[4] start increasing at the time t0 and reach a default voltage Vdft at a time t0′. However, if the output ports USB[1], USB[2], USB[3], USB[4] are respectively connected to four external electronic devices, the four external electronic devices simultaneously draw current from the circuit system 10 when the circuit system 10 is powered on, resulting in a voltage drop in the supply voltage VCC from the time t0 to the time t0′. In the worst case, the voltage drop triggers under voltage protection of other circuit systems sharing the power end PWR with the circuit system 10, which will cause function error or crash of the entire system.
Please refer to FIG. 2A, which is a schematic diagram of another circuit system 20 for preventing the voltage drop of the supply voltage VCC of the prior art. Compared to the circuit system 10, the circuit system 20 additionally includes time delay modules 200_1, 200_2, 200_3, 200_4 utilized for delaying the enable signal ENB for different periods through various combinations of capacitance and resistance to generate enable signals ENB[1], ENB[2], ENB[3], ENB[4]. In FIG. 2B, activation times of the enable signals ENB[1], ENB[2], ENB[3], ENB[4] are staggered. As a result, the switch units 100_1, 100_2, 100_3, 100_4 start functioning at different times, and therefore the supply voltage VCC no longer drops due to the over-drawn currents. However, the time delay modules 200_1, 200_2, 200_3, 200_4 include capacitors and resistors which are disadvantageous to manufacturing costs and system design flexibility.
Therefore, staggering the activation times of the switch modules more economically has been a major focus of the industry.